Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device having a buried bit line connected to a one-sidewall contact.
There is a limit to improving an integration degree of a conventional MOSFET element because a leakage current, an on-current, and a short channel effect may result as the element is ultra-miniaturized. To address such a limit, a planar channel has been replaced with a vertical channel protruding in a perpendicular direction from a substrate.
Hereafter, the structure of a conventional vertical-channel semiconductor device and concerns thereof are described in detail with reference to FIGS. 1A and 1B.
FIGS. 1A and 1B are diagrams illustrating the structure of the conventional vertical-channel semiconductor device. FIG. 1A is a perspective view of the semiconductor device, and FIG. 1B is a plan view of the semiconductor device.
Referring to FIGS. 1A and 1B, the conventional vertical-channel semiconductor device includes a plurality of pillars 11 protruding from a substrate 10, a plurality of parallel buried bit lines BBL extended along a first direction I-I′, and a plurality of parallel word lines WL extended along to a second direction II-II′ crossing over the first direction I-I′.
Specifically, a plurality of pillar structures, including a first hard mask layer 14 and the pillars 11, extend in a vertical direction from the substrate 10. Each of the pillars 11 is surrounded by a gate electrode 13, and a gate dielectric layer 12 is interposed between the pillar 11 and the gate electrode 13 as shown FIG. 1B.
The buried bit lines BBL are formed by implanting impurity ions into the substrate 10, and a trench T is formed between the neighboring buried bit lines BBL. Although not illustrated in FIG. 1A, an insulation layer for separating the neighboring buried bit lines from each other is filled in the trench T.
Each of the word lines WL connects the gate electrodes 13 of the pillars 11 arranged in the second direction II-II′, and is extended to cross over the corresponding buried bit line BBL.
In accordance with the conventional vertical-channel semiconductor device, since the buried bit lines BBL are formed by implanting dopants into the substrate 10 through an ion implantation process, there is a limit in reducing the resistance of the buried bit lines BBL.
Furthermore, while the word lines WL are formed after the gate electrodes 13 are formed, the sheet resistance of the word lines WL may be increased by resistance components of the gate electrodes 13.
Furthermore, when the hard mask layer 14 and the substrate 10 are etched to form the pillar structures, the pillar structures may be inclined or collapse in the fabricating process of the semiconductor device, because the pillar structures have a large aspect ratio.